The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a recess gate.
With the ultra-high integration of a semiconductor device, a threshold voltage is lowered and a refresh characteristic is degraded due to the decrease of a channel length of a cell transistor. Therefore, increasing the channel length of the cell transistor is needed. Increasing the channel length is achieved through a recess gate process in which a predetermined portion of an active region of a semiconductor substrate is etched to form a recess gate.
FIGS. 1A to 1E illustrate sectional views of a typical method for fabricating a semiconductor device with a recess gate. Referring to FIG. 1A, an isolation structure 12 is formed to define an active region of a substrate 11.
A sacrificial oxide layer 13 and a hard mask layer 14 are formed on the substrate 11 in sequence. For example, the hard mask layer 14 is formed in a double-layer structure including a polysilicon layer 14A and a silicon oxynitride (SiON) layer 14B are stacked on the sacrificial oxide layer 13.
A photoresist pattern 16 is formed over the hard mask layer 14 to define a region where a recess pattern will be formed. Between the hard mask layer 14 and the photoresist pattern 16, an anti-reflective coating layer 15 is interposed to prevent the reflection during a photo-exposure.
Referring to FIG. 1B, the SiON layer 14B is etched using the photoresist pattern 16 as an etch mask. Then, the photoresist pattern 16 and the anti-reflective coating layer 15 are removed. Reference numeral 14X represents a first hard mask pattern including the SiON layer pattern 14B1 and the polysilicon layer 14A.
Referring to FIG. 1C, the polysilicon layer 14A is etched using the SiON layer pattern 14B1 as an etch barrier. The etching of the polysilicon layer 14A is performed until the sacrificial oxide layer 13 is exposed. During the etching of the polysilicon layer 14A, a portion of the sacrificial oxide layer 13 may be etched. Reference numeral 14Y represents a second hard mask pattern including the SiON layer pattern 14B1 and a polysilicon layer pattern 14A1.
Referring to FIG. 1D, the SiON layer pattern 14B1, is removed. The exposed sacrificial oxide layer 13A is etched using the polysilicon layer pattern 14A1 as an etch barrier to expose the substrate 11. Reference numeral 13A represents a sacrificial oxide layer pattern.
Referring to FIG. 1E, the exposed substrate 11 is anisotropically etched using the polysilicon layer pattern 14A1 and the sacrificial oxide layer pattern 13A as an etch barrier, thereby forming a recess pattern 100 having a vertical profile. During this process, the polysilicon layer pattern 14A1 may be all removed. Reference numeral 11A represents a patterned substrate.
A gate is formed over the recess pattern 100 formed through the above-described processes to increase the channel length of the cell transistor, which makes it possible to improve device characteristics such as threshold voltage, refresh, etc. However, as recently a space between patterns is reduced with the advance of ultra-high integration of a semiconductor device, the same phenomenon (i.e., the reduction of a space between recess patterns) is likely to occur during forming of a recess pattern. The reduction between the recess patterns may cause the recess patterns to be bridged together. In addition, a height difference between an isolation structure and an active region frequently occurs during the formation of the isolation structure in a typical recess gate process. The height difference may lead to more frequent occasions of the bridge formation between the recess patterns. The bridge formation will be more fully described with reference to FIGS. 2A to 2C below.
FIGS. 2A to 2C illustrate sectional views showing limitations which may occur in fabricating a typical semiconductor device with a recess gate. Referring to FIG. 2A, an isolation structure 22 is formed in a semiconductor substrate 21 to define an active region. As for more detailed description of the formation of the isolation structure 22, a pad oxide layer (not shown) and a pad nitride layer (not shown) are formed in sequence on the semiconductor substrate 21, and patterned into a predetermined structure. An exposed portion of the semiconductor substrate 21 is etched using the patterned pad oxide and nitride layers as a mask to form trenches. An insulating layer is formed on the entire surface of the above resultant substrate structure, and polished using the patterned pad nitride layer as a polish stop layer to form the isolation structure 22 that fills the trenches. The pad nitride layer is generally removed. Therefore, the active region of the semiconductor substrate 21 is located lower than the isolation structure 22, resulting in the height difference therebetween over the resultant substrate structure.
A sacrificial oxide layer 23 and a polysilicon layer 24 for use in a hard mask are sequentially formed on the above resultant substrate structure having the height difference between the active region of the semiconductor substrate 21 and the isolation structure 22. Due to the height difference, a portion of the polysilicon layer 24 disposed over the active region also becomes lower than a portion thereof disposed over the isolation structure 22.
Referring to FIG. 2B, the polysilicon layer 24 is etched to form a patterned polysilicon layer 24A. At this time, the portion of the polysilicon layer 24 (see FIG. 2A) over the active region is more actively etched than the portion of the polysilicon layer over the isolation structure 22. Consequently, as illustrated in FIG. 2B, a portion of the patterned polysilicon layer 24A over the active region has a weaker structure than the portion of the patterned polysilicon layer 24A over the isolation structure 22.
Accordingly, as illustrated in FIG. 2C, the sacrificial oxide layer 23 and the semiconductor substrate 21 are etched using the patterned polysilicon layer 24A as an etch barrier to form a recess pattern 200. Reference numeral 23A and 21A represent a patterned sacrificial oxide layer and a patterned substrate, respectively. As reference numeral 24B indicates, the portion of the patterned polysilicon layer 24A disposed over the active region is highly likely to be removed during the etching for forming the recess pattern 20 due to the aforementioned structural weakness. For this reason, the patterned polysilicon layer 24A may not act as an effective hard mask (i.e., etch barrier). Therefore, recesses of the recess pattern 200 are likely to be bridged together. Alternatively, it may be difficult to adjust a critical dimension (CD) or a profile of the recess pattern 200.